// Copyright (C) 1953-2020 NUDT
// Verilog module name - ts_injection_management 
// Version: TIM_V1.0
// Created:
//         by - fenglin 
//         at - 10.2020
////////////////////////////////////////////////////////////////////////////
// Description:
//         injection management of time-sensitive packet
//             - use a simple dual port ram to cache descriptor of time-sensitive packet; 
//             - judge whether descriptor of each TS traffic is underflow;
//             - read descriptor of time-sensitive packet according to injection addr.
///////////////////////////////////////////////////////////////////////////
 
`timescale 1ns/1ps

module st_injection_management
(
        i_clk                          ,
        i_rst_n                        ,
       
        iv_addr                        ,         
        iv_wdata                       ,         
        i_wr                           ,      
        i_rd                           ,                      
        o_wr                           ,      
        ov_addr                        ,      
        ov_rdata                       ,          
       
        iv_ts_descriptor,
        i_ts_descriptor_wr,
        iv_ts_descriptor_waddr,
        
        iv_ts_injection_addr,
        i_ts_injection_addr_wr,
        o_ts_injection_addr_ack,
        
        ov_ts_descriptor,
        o_ts_descriptor_wr,
        i_ts_descriptor_ack,
        
        ov_st_stream_state
);

// I/O
// clk & rst
input                  i_clk;
input                  i_rst_n; 

input       [18:0]     iv_addr;                         
input       [31:0]     iv_wdata;                        
input                  i_wr;         
input                  i_rd;         

output                 o_wr            ;          
output      [18:0]     ov_addr         ;       
output      [31:0]     ov_rdata        ;
// writting ts descriptor to ram
input      [11:0]      iv_ts_descriptor;
input                  i_ts_descriptor_wr;
input      [4:0]       iv_ts_descriptor_waddr;
//ts injection addr
input      [4:0]       iv_ts_injection_addr;
input                  i_ts_injection_addr_wr;
output                 o_ts_injection_addr_ack;
// output ts descriptor
output     [11:0]      ov_ts_descriptor;
output                 o_ts_descriptor_wr;
// FLM get ts descriptor to look up table 
input                  i_ts_descriptor_ack; 
//ack signal of reading ts descriptor
//output reg [31:0]      ov_ts_rd_ack;  
//count ts descriptor
output     [31:0]      ov_st_stream_state; 
command_parse_and_encapsulate_sim command_parse_and_encapsulate_sim_inst(
.i_clk                    (i_clk                ),                
.i_rst_n                  (i_rst_n              ),      
                                                
.iv_addr                  (iv_addr              ),         
.iv_wdata                 (iv_wdata             ),         
.i_wr                     (i_wr                 ),      
.i_rd                     (i_rd                 ),      
                                                
.o_wr                     (o_wr                 ),      
.ov_addr                  (ov_addr              ),      
.ov_rdata                 (ov_rdata             )        
);

st_dbufid_cache st_dbufid_cache_inst(
.i_clk                   (i_clk                        ),
.i_rst_n                 (i_rst_n                      ),
                        
.iv_ts_descriptor        (iv_ts_descriptor           ),
.i_ts_descriptor_wr      (i_ts_descriptor_wr         ),
.iv_ts_descriptor_waddr  (iv_ts_descriptor_waddr  ),
                         
.iv_ts_injection_addr    (iv_ts_injection_addr         ),
.i_ts_injection_addr_wr  (i_ts_injection_addr_wr       ),
.o_ts_injection_addr_ack (o_ts_injection_addr_ack      ),
                         
.ov_ts_descriptor        (ov_ts_descriptor                   ),
.o_ts_descriptor_wr      (o_ts_descriptor_wr                 ),
.i_ts_descriptor_ack     (i_ts_descriptor_ack                ),

.ov_st_stream_state      (ov_st_stream_state   ),
.o_ts_underflow_error_pulse(),
.tim_state()    
);   	
endmodule